In a recent technical publication titled “Vertical FET Optimization at Angstrom Nodes: A Comparative Study With Horizontal FET,” a group of researchers from POSTECH and the Georgia Institute of Technology delved into the realm of advanced semiconductor technologies. This study marks a significant milestone, introducing two innovative vertical FET (VFET) structures and conducting a comprehensive quantitative evaluation to compare their performance with two types of horizontal FETs (HFET): nanosheet FET (NSFET) and forksheet FET (FSFET) tailored for Angstrom nodes.
The researchers found that the conventional VFET design, VFETCON, exhibited a larger footprint compared to FSFET, resulting in subpar performance even after gate length optimization. Contrarily, the novel fork-shaped channel VFET (VFETFS) showcased a remarkable 10.5% reduction in effective area compared to VFETCON, achieving a smaller footprint than FSFET while maintaining a large contact poly pitch (CPP). Notably, VFETFS demonstrated improved performance over VFETCON due to reduced capacitance, although it showcased a lower drive current (Ion) than FSFET with a smaller CPP. Strategies focusing on enhancing the silicide area effectively boosted Ion by mitigating parasitic resistance, enabling NFET VFETFS to outperform FSFET, particularly in terms of drive current.
Furthermore, the study highlighted the importance of secondary device architectures, such as VFETFS with back-side contact (VFETBSC), in reducing footprint size, lowering parasitic RC, and enhancing heat dissipation with a substantial back-side contact area. VFETBSC showcased a smaller effective area requirement compared to FSFET with a 42 nm CPP, demonstrating superior average performance for both N and PFET configurations when compared to FSFET. However, it was observed that for PFET, VFETFS with enlarged silicide areas exhibited decreased performance compared to FSFET due to the heightened impact of performance degradation under non-stress conditions.
The research outcomes, as detailed in the technical paper published in the IEEE Journal of the Electron Devices Society, shed light on the promising potential of VFET structures in advancing semiconductor technologies. By offering insights into the performance trade-offs and optimization strategies between vertical and horizontal FET designs, this study contributes valuable knowledge to the field of semiconductor device engineering. The investigation into VFETFS and VFETBSC architectures provides a glimpse into the future possibilities of semiconductor device miniaturization, performance enhancement, and heat management.
Key Takeaways:
– Vertical FET (VFET) structures, particularly VFETFS and VFETBSC, exhibit promising performance metrics compared to traditional horizontal FET designs.
– Strategies focusing on enhancing silicide areas can effectively improve drive current (Ion) and overall device performance in VFET configurations.
– Secondary device architectures like VFETBSC offer reduced footprint sizes, lower parasitic resistance-capacitance (RC) effects, and improved heat dissipation capabilities.
– The study underscores the importance of exploring novel device architectures and optimization techniques to drive advancements in semiconductor technologies.
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